The invention relates to a random access memory (RAM) including a multiplicity of memory cells that each have a memory device with a memory content which establishes a logic state that can be changed by a control voltage.
In numerous applications, an electronic device, such as a personal computer, for example, requires a RAM having a defined memory content in order to start. In the case of a personal computer, this defined memory content is, for example, the operating system BIOS (Basic Input/Output System). During use, the memory content is generally overwritten and modified. Under special circumstances, for example, whenever rebooting of the device is required, the original memory state must be restored in the RAM. This has previously been accomplished by performing the time-consuming operation of rewriting the RAM from an external source. In the case of a personal computer, the rewriting would be performed from a hard disk. In the case of certain types of devices, for example, in portable applications, such as cellphones for instance, this rewriting operation usually cannot be accomplished by the user alone.
There is therefore a need to rewrite the contents of a RAM to the original memory state in a manner that can be accomplished at any time and at a high speed without a great amount of time having to be expended.
It is accordingly an object of the invention to provide a RAM which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a random access memory that includes a plurality of memory cells. Each one of the plurality of the memory cells has a first memory device with a memory content defining a logic state. Each one of the plurality of the memory cells receives a first control voltage for changing the memory content of the first memory device. At least some of the plurality of the memory cells have a second memory device with a memory content defining a logic state. Each one of the plurality of the memory cells which include a second memory device receive a second control voltage for impressing the logic state of the second memory device on the first memory device. The second control voltage is an enforced control voltage that is different from the first control voltage.
In accordance with an added feature of the invention, the RAM includes a plurality of word lines and a plurality of bit lines, and each one of the plurality of the memory cells is formed as a DRAM memory cell. The second memory device of one of the plurality of the memory cells having a second device is connected between one of the plurality of the word lines and one of the plurality of the bit lines, and the second control voltage is greater than the first control voltage.
In accordance with an additional feature of the invention, the second memory device of one of the plurality of the memory cells includes a diode with an adapted breakdown voltage.
In accordance with another feature of the invention, the second memory device of one of the plurality of the memory cells includes a transistor with an adapted turn-on voltage.
In accordance with a further feature of the invention, each one of the plurality of the memory cells has a second memory device. The second memory device of each one of the plurality of the memory cells can optionally be connected between one of the plurality of the word lines and one of the plurality of the bit lines.
In accordance with a further added feature of the invention, there is provided, a contact hole for connecting the second memory device of a selected one of the plurality of the memory cells between one of the plurality of the word lines and one of the plurality of the bit lines.
In accordance with a further additional feature of the invention, there is provided, an electronic fuse for connecting the second memory device of a selected one of the plurality of the memory cells between one of the plurality of the word lines and one of the plurality of the bit lines.
In accordance with a concomitant feature of the invention, each one of the plurality of the memory cells is formed as an FeRAM cell. One of the plurality of the memory cells includes a line, a first ferroelectric capacitor that defines the first memory device, a second ferroelectric capacitor that defines the second memory device and that is connected in parallel with the first ferroelectric capacitor, and a transistor. The second ferroelectric capacitor is connected between the transistor and the line. The first ferroelectric capacitor stores a logic state by applying a first activation voltage. The second ferroelectric capacitor stores a logic state by applying a second activation voltage. The first activation voltage is smaller than the second activation voltage. The logic state of the second ferroelectric capacitor is read out with the second control voltage, which is greater than the second activation voltage, in order to impress the logic state of the second ferroelectric capacitor on the first ferroelectric capacitor. The logic state of the first ferroelectric capacitor is variable with a control voltage that is greater than the first activation voltage and smaller than the second activation voltage. The logic state of the second ferroelectric capacitor is invariable.
In other words, xe2x80x9chidden bitsxe2x80x9d are used to store a defined memory content in the RAM itself in an easy and quickly recoverable manner. The invention specifically envisages storing an additional hidden bit at least in some of the memory cells of the RAM. This hidden bit may be defined, for example, by wiring or mask programming or else by the state of an additional ferroelectric storage capacitor.
Generally, the hidden bit is provided by an additional memory device in the memory cell of the RAM which can be activated by an enforced control voltage, which differs from the control voltage of the memory cell. What is important here is that an originally established memory content of the RAM can be recovered in a simple way by applying one and the same enforced control voltage to the memory cells concerned. The enforced control voltage ensures that the memory contents of the memory cells can be reset to the original contents at a higher speed than was previously possible by time-consuming rewriting of the memory content of the memory cells. The only precondition is that the enforced control voltage differs in a defined way from the control voltage with which the logic state of the memory cells of the RAM is usually changed or defined.
The modified RAM having hidden bits can be a DRAM or an FeRAM (Ferro-Electric Random Access Memory).
In the case of the DRAM, the additional memory device establishing the hidden bit includes an additional component between the word line and the bit line of the DRAM memory cell. The additional component is activatable by means of an enforced control voltage which is greater than the normal control voltage on the bit line. This additional component may either be a diode with an adapted breakdown voltage or a transistor with an adapted turn-on voltage.
To easily produce the RAM modified with hidden bits, all of its memory cells are preferably provided with the additional memory device in the form of the additional component, which can then optionally be connected to the word and bit lines. This optional connection preferably takes place by means of a contact hole, which is either made or not made.
In the case of a RAM in the form of an FeRAM, by contrast with the aforementioned DRAM, the information of a hidden bit can also be modified. This is achieved by connecting the additional memory device between the word line and the bit line of the DRAM memory cell and by providing first and second ferroelectric capacitors. The first and second ferroelectric capacitors each store a bit by applying an activation voltage Vc1 and Vc2 (Vc1 less than Vc2), respectively, by means of a selection transistor. It is possible for the bit (hidden bit) of the second ferroelectric capacitor C2 to be read out with a voltage (enforced control voltage) U greater than Vc2 in order to impress the defined logic state on the first capacitor during the subsequent rewriting of the memory cell. The bit of the first capacitor C1 is variable with a voltage Vc1 less than U less than Vc2, but the bit of the capacitor C2 is invariable.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a random access memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.